In this paper, the chief undertaking is to cipher the exchanging velocity of a CMOS inverter, which is defined as the 90-10 autumn clip and to look into how the autumn clip is affected by: a ) the size ( width ) of the transistors, B ) the fan-out of the inverter, degree Celsius ) the power supply electromotive force and vitamin D ) the channel length. Picture 1 shows a CMOS inverter.

The 90-10 autumn clip is related to some electrical capacities listed supra. Merely the electrical capacities that are connected to the end product electromotive force ( Vo ) should be considered. Csbp, Csbn are instead shorted out. Cgsp, Cgsn are attached to the input terminus and driven straight from the beginning. Assume beginning charges and discharges them about outright, so they can be ignored as the bash non impact the shift clip.

Cdbp and Cdbn are body-drain electrical capacities and electromotive force dependant. CL is assumed to be independent of electromotive force which represents the capacitive burden.

Assume the input electromotive force switches outright from logic low to logic high. The end product will hold to dispatch CL ( or Cequiv, if there are some fan-out inverters ) from NMOS. The current flows through the PMOS transient will be ignored compared to the electrical capacity discharge current.

Therefore, the entire 90-10 autumn clip for a CMOS inverter harmonizing to the above premises is

The computing machine plan to acquire these figures is explained in subdivision 4 – Appendix 1, which shows the code-design and the analysis. Here are the consequences obtained from my plan.

In this assignment, the undermentioned secret plans are shown.

1: The 90-10 autumn clip Vs the NMOS breadth for the channel length LMn = LMp = 1um, VDD =2.5 Vs and with a individual indistinguishable inverter ( i.e. same as that of the driver as the burden ) .

2: The consequence of ‘fan out ‘ on exchanging velocity. Assume LMn = LMp = 1um, VDD =2.5V, Wn=1 um, with n indistinguishable inverter

3: The consequence of the supply electromotive force on exchanging velocity. Assume LMn = LMp = 1um, Wn=1 um, with 1 indistinguishable inverter. Assumes VT & A ; gt ; 0.1VDD, VT=0.4 for NMOS, therefore VDD & A ; lt ; 4 V

4: The old 3 secret plans with different channel length.

Here are the consequences:

Figure 1: The 90-10 autumn clip Vs the NMOS breadth

Note: the channel length LMn = LMp = 1um, VDD =2.5 Vs and with a individual indistinguishable inverter ( i.e. same as that of the driver as the burden )

Figure 2: The consequence of ‘fan out ‘ on exchanging velocity

Note: presume LMn = LMp = 1um, VDD =2.5V, Wn=1 um, with n indistinguishable inverter

Figure 3: The consequence of the supply electromotive force on exchanging velocity

Note: presume LMn = LMp = 1um, Wn=1 um, with 1 indistinguishable inverter

Assumes VT & A ; gt ; 0.1 VDD, VT=0.4 for NMOS, therefore VDD & A ; lt ; 4 V

Figure 4: The 90-10 autumn clip Vs the NMOS breadth

With different channel length

Note: VDD =2.5 Vs and with a signal indistinguishable inverter. LMn=LMp=1,2,4,8um

Figure 5: The consequence of ‘fan out ‘ on exchanging velocity

with different channel lengthes

Note: presume LMn= LMp=1, 2, 4, 8um ; VDD =2.5V ; Wn=4 um,

with n indistinguishable inverter

Figure 6: The consequence of the supply electromotive force on exchanging velocity

Note: presume LMn = LMp = 1, 2, 4, 8um, Wn=4 um, with 1 indistinguishable inverter

Assumes VT & A ; gt ; 0.1 VDD, VT=0.4 for NMOS, therefore VDD & A ; lt ; 4 V

## Section 3 Explanation of the consequences

Harmonizing to the entire 90-10 autumn clip equation:

There following remarks can be made:

First, the exchanging velocity lessenings linearly in proportion to the burden electrical capacity. However, by altering the breadth to alter the burden electrical capacity, the autumn clip will non be additive, as the breadth appears someplace else in the equation ( See figure 1 ) .

Second, the shift velocities addition in proportion to Kn ( =uCox ) . Hence, it shows the advantage of both high mobility and thin oxide.

Third, a big device which has big W/L ratio gives faster exchanging velocity, but will treat higher internal electrical capacity, increasing CL. If CL becomes dominated by the breadth of the transistor, there is no velocity advantage to be gained in increasing the size of the transistor. that is, CL increases in proportion to W which cancels the addition in Kn ( See figure 1 ) .

Fourthly, increasing the positive supply can do shorter exchanging times. This is why interior decorators have been loath to cut down the supply electromotive force from 5V as devices are scaling down- but keeping 5V supply tracks whilst scaling down device size increasing the internal electric field strength and via medias dependability and device life-time ( See figure 3 ) . In theorem, high supply electromotive force means high power dissipation.

Finally, if we assume that interconnect electrical capacity is little compared to that of the MOSFET device, we consider the burden to be dominated by the electrical capacity of the undermentioned MOSFETs ( assume fan-outs of N ) :

so

This highlighted the importance of short channel length ( L ) , ( See figure 4-6 ) .

After analysing the equation above, the figures shown in subdivision 2 will clearly demo the tendency.

As we can see from the old subdivision, set the channel length to be the initial value, which is 1um. The 90-10 autumn clip decreases when the NMOS breadth additions, for the same power supply and goaded inverters ( See figure 1 ) . It increases linearly when the figure of fan-outs additions, for the same breadth and power supply ( See figure 2 ) and it decreases when the supply electromotive force additions, for the same breadth and goaded inverters ( See figure 3 ) .

Then, utilize different channel lengths to detect how the old factors will impact the autumn clip. See the 90-10 autumn clip Vs the NMOS breadth once more, the autumn clip increases with the channel length, for the same power supply and goaded inverters ( See figure 4 ) . See the consequence of ‘fan out ‘ on exchanging velocity Vs the NMOS breadth once more, the autumn clip besides increases with the channel length, for the same power supply and breadth ( See figure 5 ) . See the consequence of the supply electromotive force on exchanging velocity once more, the autumn clip so increases with the channel length, for the same power supply and goaded inverters ( See figure 6 ) .

In brief, in order to maintain the autumn clip little and besides sing about the commercial factors, in pattern, the maximal breadth and length may be 6 to 8 um. The maximal fan-out may be approximately 6 to 8. The supply electromotive force may be about 5 Vs.

When speaking about the semiconducting material engineering, usually, the Moore ‘s jurisprudence is used to foretell the hereafter size. The jurisprudence is found by Gordon Moore, the honorary president. Moore ‘s Law describes a long-run tendency in the history of calculating hardware, in which the figure of transistors that can be placed cheaply on an integrated circuit has doubled about every 1.5-2 old ages.

SiO2 have been used as the gate oxide stuff for decennaries due to its manufacturability and its efficiency can be kept when the thickness is reduced. As transistors have decreased in size, the thickness of the Si dioxide gate insulator has steadily decreased to increase the gate electrical capacity and thereby drive current and device public presentation.

However, as clip went on, the thickness about reaches its physical restriction. If SiO2 is still used as the gate oxide, the current escape will be really large and it can non work decently. If the power supply is increased to do it work, the power dissipation will besides be increased significantly. Hence, it is necessary to happen stuffs that have high dielectric invariable so that the thickness can be ensured and the current escape will be low.

## Section 4 Appendix 1: Code design

## 4.1 The thought to plan the codification

The chief thought to plan the codification is get downing from the 90-10 autumn clip equation. The first measure is happening all the measures mentioned in that equation. Then, looking for the measures already known ( given in the press release ) . After that, seek to work out the unknown measures through other equations which relates to the 90-10 autumn clip equation. If the related equation brings in some new measures, merely happen out another related equation to work it out. Until all the measures are known expect the variables such as the size ( width ) of the transistor.

## 4.2 The flow chart of the design

Harmonizing to the design thought, the following follow char can be drawn. Acutely, the codification is the contrary of the flow chart. Get downing from the measures that we already know and the variables, calculate the basic equations until the 90-10 autumn clip equation can be represent by all the variables and invariables.

Picture 2: the design thought ( change by reversal the way is the flow confab )

Note: All the symbols used in this image will be explained in subdivision 4.3 and all the equations given between each next block will besides be shown.

## 4.3 The account of the flow chart

Get downing with the undermentioned equation:

— — ( 1 )

Harmonizing to the talk notes, the negligible current will flux through PMOS during this transistor compared to the electrical capacity discharge current. Therefore, the equation above will be:

— — ( 2 )

The measures mentioned above include: CL, Kn, VDD, VTn, Ln and Wn. VTn is known as 0.4 Volt harmonizing to the given appendix. VDD, Ln and Wn are the variables. Merely CL and Kn should be considered.

Then, start with the first unknown measure, CL. Note that for an inverter feeding n other inverters:

— — ( 3 )

Where:

— — ( 4 )

— — ( 5 )

See equation ( 4 ) , is given in the press release. Then, is tried to be solved.

— – ( 6 )

Where:

— — ( 7 )

— — ( 8 )

— — ( 9 )

for NMOS is. for NMOS is

See equation ( 7 ) ,

at 300K. — — ( 10 )

cm^ ( -6 ) — – ( 11 )

— — ( 12 )

— — ( 13 )

Therefore, every variable is known so that is known except the breadth, channel length of the transistor and the power supply electromotive force. The procedure to cipher is similar to the procedure to cipher.

What should be paid attending to is that: Wp can be converted to a map of Wn harmonizing to the mobility ratio, which is:

— — ( 14 )

When Ln=Lp,

— — ( 15 )

and are given in the press release. Hence, the breadth ratio is known.

See equation ( 4 ) once more,

— — ( 4 )

is tried to be solved.

— — ( 16 )

for NMOS is.

Hence, merely the size ( breadth ) is unknown for. Thus is represented by the variables and invariables.

See equation ( 5 ) ,

— — ( 5 )

The procedure to cipher is the same to cipher.

is tried to be solved.

— — ( 17 )

Where,

— — – ( 18 )

are given in the manus out, Hence, is known merely related to W and L. Thus, CL can be represented by all the variables and invariables.

See the procedure to acquire Kn of the 90-10 autumn clip equation.

— — ( 19 )

and the mobility are given in the manus out, Hence, Kn is known.

To sum up, the 90-10 autumn clip equation can be represented as required.

## 4.4 The computing machine plan codifications

The chief undertaking is to cipher the exchanging velocity of a CMOS inverter,

which is defined as the 90-10 autumn clip and to look into how the

autumn clip is affected by:

a ) the size ( width ) of the transistors — — W

B ) the fan-out of the inverter — — Liter

degree Celsius ) the power supply electromotive force — — N

vitamin D ) the channel length — — VDD

map t_fall = falltime ( W, L, N, VDD )

The measures given in the press release

V_Tn = 0.4 ; NMOS long channel threshold electromotive force at Vbs=0, V

u_NOMS_Mo = 2.84*10^ ( -2 ) ; NMOS mobility, m^2/Vsec

E_ox = 3.9 ; Relative permittivity of SiO2

E_0 = 8.85*10^ ( -12 ) ; Permittivity ( or dielectric changeless ) , F/m

t_ox_n = 5.6*10^ ( -9 ) ; NMOS gate oxide thickness, m

C_GDO_n = 4.65*10^ ( -10 ) ; NMOS gate-drain convergence electrical capacity, F/m

C_GDO_p = 5.59*10^ ( -10 ) ; PMOS gate-drain convergence electrical capacity, F/m

Ratio = ( 2.4*10^ ( 38 ) *10^ ( 12 ) ) / ( ( 1.5*10^16 ) ^2 ) ; Ration = Na * Nd / ( Ni ) ^2

V_bi = 0.025*log ( Ratio ) ; The physique in electromotive force

C_J0_n = 1.7*10^ ( -3 ) ; NMOS zero prejudice majority junction underside electrical capacity per m^2 of junction country, F/m^2

C_J0_p = 1.9*10^ ( -3 ) ; PMOS zero prejudice majority junction underside electrical capacity per m^2 of junction country, F/m^2

C_JSW0_n = 3.9*10^ ( -10 ) ; NMOS zero prejudice majority junction sidewall electrical capacity per m of junction country, F/m

C_JSW0_p = 4.2*10^ ( -10 ) ; PMOS zero prejudice majority junction sidewall electrical capacity per m of junction country, F/m

C_W = 10^ ( -15 ) ; Interconnect wire electrical capacity, F

Lp = L ; Channel length Lp=Ln=L=1um ( initial )

Ln = L ;

Wn = W ; Channel width W=1um ( initial )

Wp = 2.84. *Wn ; u_NOMS_Mo/p_NOMS_Mo = Wp/Wn =2.84

Y = 10^ ( -6 ) ; Length of drain, initial value is 1um

V_H = 0.9. * VDD ; Voltage swing of involvement, 90 VDD

V_L = 0.1. * VDD ; Voltage swing of involvement, 10 VDD

ADn = Wn * Y ; NMOS country of the drain

ADp = Wp * Y ; PMOS country of the drain

PDn = 2. *Wn + Y ; NMOS side wall ( margin ) of the drain

PDp = 2. *Wp + Y ; PMOS side wall ( margin ) of the drain

K_eqn= ( 2.* ( V_bi^ ( 0.5 ) ) ./ ( V_H-V_L ) ) . * ( ( ( acrylonitrile-butadiene-styrene ( V_bi+V_H ) ) .^ ( 0.5 ) ) – ( ( acrylonitrile-butadiene-styrene ( V_bi + V_L ) ) .^ ( 0.5 ) ) ) ;

K_egp = K_eqn ; Dimensionless coefficient to cipher an equvalent big signal electrical capacity

C_dbn1 = K_eqn.* ( ADn. *C_J0_n + PDn. *C_JSW0_n ) ; NMOS drain-body junction

C_dbp1 = K_egp.* ( ADp. *C_J0_p + PDp. *C_JSW0_p ) ; PMOS drain-body junction

C_gdon2 = C_GDO_n. *Wn ; NMOS gate-drain convergence

C_gdop2 = C_GDO_p. *Wp ; PMOS gate-drain convergence

Co = ( E_ox * E_0 ) /t_ox_n ;

C_gn2=Co.*Wn. *Ln ; NMOS gate electrical capacity

C_gp2=Co.*Wp. *Lp ; PMOS gate electrical capacity

CL_interconnect = C_dbn1 + C_dbp1 + 2. * ( C_gdon2 + C_gdop2 ) + C_W ;

thrust electrical capacity

CL_device = 2. * ( C_gdon2 + C_gdop2 ) + C_gn2 + C_gp2 ;

individual fan-out electrical capacity

C_L =CL_interconnect + N.*CL_device ; The effectual capacitior burden

Kn = u_NOMS_Mo*Co ;

the autumn clip

t_fall= ( ( 2.*C_L ) ./ ( Kn.* ( VDD-V_Tn ) ) ) .* ( L./W ) .* ( ( ( V_Tn-0.1.*VDD ) ./ ( VDD-V_Tn ) ) +log ( ( 2.* ( VDD-V_Tn ) -0.1.*VDD ) ./ ( 0.1. *VDD ) ) ) ;

## Section 5 Appendix 2: Time sheet

Personal clip sheet

For each entry, bespeak how satisfied you we that the clip spent was productive. 1=low, 5=high.

Date

Time ( hour )

Intended ends

Achievement ( click one )

1

2

3

4

5

2009-10-17

About 2

Review talk notes

## –

2009-10-22

About 2

Read this assignment and book 3.6

## –

2009-10-23

About 2

Analyze the job

Start to composing subdivision 1

## –

2009-10-24

About 4

Design the codification

## –

2009-10-25

About 4

Writing subdivision 4

## –

2009-10-26

About 4

Mat lab codification

Consequences and account

## –

2009-10-27

About 4

Mat lab codification

Consequences and account

## –

2009-10-28

About 2

Check the study and alter some errors